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CT60 and related things BBS
| Side note |
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Posted by: Instream
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Jun,07.2010-19:42
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Just wanted to point out that the Ethernat registers were put at 0x80000000 because 0x80000000 to 0xBFFFFFFF was the only area which is not either reserved, uses cache+burst or is dedicated to the SDRAM (according to chg.pdf). And no CTPCI with enormous memory map requirements existed then. :P
The Supervidel currently uses 128MB at 0xA0000000 (don't want cache nor burst), with a few hundred bytes of control regs at 0x8001xxxx. But the 128MB RAM placement is of course movable since the SV is not released yet.
/Torbjörn
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[All messages in this thread] [Start new thread]
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Topic
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Posted by
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Date
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Some news...
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Didier Méquignon
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Jun,07.2010-13:17
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Re: Some news...
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mikro
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Jun,07.2010-16:16
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Re: Some news...
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Didier Méquignon
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Jun,07.2010-17:29
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Re: Some news...
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mikro
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Jun,07.2010-19:01
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Re: Some news...
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Didier Méquignon
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Jun,08.2010-12:45
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Re: Some news...
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mikro
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Jun,08.2010-13:31
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Side note
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Instream
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Jun,07.2010-19:42
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Re: Side note
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Didier Méquignon
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Jun,08.2010-12:52
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Re: Side note
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Instream
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Jun,08.2010-21:23
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Re: Side note
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Didier Méquignon
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Jun,09.2010-12:57
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Re: Side note
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Didier Méquignon
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Jun,11.2010-12:54
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Re: Side note
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Didier Méquignon
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Jun,15.2010-19:02
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Re: Side note
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Ektus
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Jun,18.2010-16:46
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What's the anti-troll code?
That's your personal code to be able to add comments and messages on the dhs.nu site.
Don't have a code or forgot it? Fix it here.
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