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Re: DSP SSI question
Posted by: mikro Jun,24.2024-10:44 

That's a good guess. The UM gives some hints as well:


"The interrupt controller jams the two instructions into the instruction stream and releases the PC, which is used for the next instruction fetch. The next interrupt arbitration is then begun.

If neither instruction is a change of program-flow instruction (i.e., a JSR), the state of the machine is not saved on the stack, and a fast interrupt is executed."

So that "i.e." could be interpreted as not the sole option. However later:


"A long interrupt is formed if one of the interrupt instructions fetched is a JSR instruction. The PC is immediately released, the SR and the PC are saved in the stack, and the jump instruction controls where the next instruction is fetched from. While either an unconditional jump or conditional jump can be used to form a long interrupt, they do not store the PC on the stack; therefore, there is no return path."

So yes, JMP forms a long interrupt (Thadoss is therefore not correct in his interpretation: "From what I understand of the Motorola DSP doc, the jmp in the 2 instructions interrupt vector generates a fast interrupt, not a long interrupt") but the PC is not stored on the stack. Hmm.







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Topic Posted by  Date 
DSP SSI question Thadoss/Dune Jun,10.2024-23:34
  Re: DSP SSI question mikro Jun,11.2024-08:49
  Re: DSP SSI question tat Jun,20.2024-17:41
    Re: DSP SSI question mikro Jun,24.2024-10:44
      Re: DSP SSI question Thadoss/Dune Jun,24.2024-21:51
      Re: DSP SSI question Thadoss/Dune Jun,24.2024-21:58


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