|
|
Atari coding BBS
| Re: DSP extern memory extra cycles |
|---|
|
Posted by: mikro
|
Jan,05.2012-08:49
|
This is what I wrote to Thomas Bergstrom when he had asked me about DSP cycles:
======
I use this method, derived from DSP UM and my thoughts:
- internal memory: 0 cycles
- external memory: 1 cycle
- most instructions: 2 cycles (better check these numbers, I didn't do this
for years)
Then, DSP is able to execute one external access + other internal access in
one go. So, if you run your instruction from internal P, referencing
internal X and/or Y (doesn't matter if in one or one + parallel moves
instruction), it still takes 2 cycles. You can even place your instruction
into external P memory and it still takes 2 cycles. Then, for every
additional external reference I add one (or two, I'm really not sure how
many cycles is external access, but I guess it's really one)... so, running
instruction from external P? +0 (see earlier). Referencing external X? +1
Referencing external Y? +1 again. So in the worst case:
mpy x0,y0,a x:(r0)+,x0 y:(r4)+,y0
it could take 2 (instr timing) + 0 (external P) + 1 (external X) + 1
(external Y) = 4 cycles. And don't forget, some addressing modes ((r0)-,
IIRC, for example) add additional cycle! So you must not only check
instruction itself (mpy) but also to pay attention what do you do in
parallel moves, not everything it's only about internal/external
referencing.
Even if this wouldn't be 100% correct, it's definitely right / rational
approach, avoid external references as much as possible. In fact,
calculating cycles for DSP is pretty trivial, comparing to 030.
> This was my thoughts aswell, but where can you find this info??
>56KUM says that insrtuction timing is "2+mv" where mv = ea + axy.
>ea = 0 for postincrement/decrement, in the example above.
axy = "External memory accesses require additional clock cycles according to the number of wait states programmed into BCR". In falcons case, BCR is set to 0, meaning 0 wait states. This would mean that even if you have P, X and Y external it is 3 * 0 = 0 in penalty. I can not find any info that says different.
2.2 ADDRESS BUSES
Addresses are specified for internal X data memory and Y data memory on two, unidirec-
tional, 16-bit buses — X address bus (XAB) and Y address bus (YAB). Program memory
addresses are specified on the bidirectional program address bus (PAB). External mem-
ory spaces are addressed via a single 16-bit, unidirectional address bus driven by a three-
input multiplexer that can select the XAB, the YAB, or the PAB. Only one external memory
access can be made in an instruction cycle. There is no speed penalty if only one external
memory space is accessed in an instruction cycle. If two or three external memory spaces
are accessed in a single instruction, there will be a one- or two-instruction-cycle execution
delay, respectively. A bus arbitrator controls external access.
|
[All messages in this thread] [Start new thread]
What's the anti-troll code?
That's your personal code to be able to add comments and messages on the dhs.nu site.
Don't have a code or forgot it? Fix it here.
|
