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Re: read/write cycles on 68000
Posted by: Kalms May,14.2006-01:22 

on 68000:
ADDX.W dn,dm is 4 cycles
ADDX.L dn,dm is 8 cycles

There is no instruction on the 68000 that takes less than 4 cycles to execute, and because the bus interface is set up the way it is on the ST (CPU can do one memory access every 4 cycles), the minimum execution time for a sequeunce of instructions is equivalent to 4x the number of memory accesses (instruction+data) that are required to fulfill the operations.







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Topic Posted by  Date 
read/write cycles on 68000 mikro May,11.2006-23:02
  Re: read/write cycles on 68000 earx May,12.2006-12:13
    Re: read/write cycles on 68000 mikro May,13.2006-00:32
    Re: read/write cycles on 68000 ggn/KUA May,13.2006-21:44
      Re: read/write cycles on 68000 Kalms May,14.2006-01:22
        Re: read/write cycles on 68000 earx May,14.2006-19:34
          Re: read/write cycles on 68000 Kalms May,14.2006-19:54
          Re: read/write cycles on 68000 mikro May,15.2006-19:57
            Re: read/write cycles on 68000 gloky Jun,06.2006-19:06


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