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MegaSTe cache logic
Posted by: tobe Jul,12.2010-16:50 

The MegaSTe cache is implemented with 4 RAM chips.

- 2x 8KB SRAM to store data (one store lo-bytes, the other hi-bytes).
- 2x 8kB SRAM with compare functionality to store addresses.

Bits 14 to 23 of the memory address are compared to the content of the address cache at the address given by bits 1 to 13 of this memory address.

If the comparison succeed, the value from the data cache is returned, else there's a memory access.

What does it mean:

The address space is divided in pages of 16384 bytes.
Two addresses from two different pages can coexist in the cache only if (addr1 & 16383) != (addr2 & 16383).





[All messages in this thread]

Topic Posted by  Date 
MegaSTe cache logic tobe Jul,12.2010-16:50
  Re: MegaSTe cache logic Cyprian Jul,13.2010-00:31
    Re: MegaSTe cache logic tobe Jul,13.2010-12:06
      Re: MegaSTe cache logic Cyprian May,14.2017-12:20
  Re: MegaSTe cache logic tobe Jul,14.2010-13:42
    Re: MegaSTe cache logic Cyprian Jul,14.2010-16:55
      Re: MegaSTe cache logic tobe Jul,15.2010-10:53


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