|
|
CT60 and related things BBS
| CTPCI new CPLD |
|---|
|
Posted by: Rodolphe
|
Dec,24.2011-14:15
|
There is a version 1G of the CTPCI CPLD on my web site. www.powerphenix.com
Please try it if you can help or see some new behaviors, please inform here.
This corrects the PCI arbiter.
Now the PCI cards (i test with the USB) get correctly the PCI bus to transfer.
This solves the problem of unstability.
But the Parity error/target abort stills.
But now the tests and test software are stable, what will seriously help to find the problem.
On logic analyser I see many retries from PLX when USB is master and access PLX, what may be possible because it is the natural method to let time for PLX to get the local 060 bus.
Many transactions are Target Disconnect with data transfer (single) (do not confuse with Target Abort).
But now my problem is to trigg the PERR line...and I have no activity on PERR line.
I asked Didier to verify that the bit in the command register of each (PLX & USB)is well set.
Actually I have no idea why the problem should be on hardware because the PCI arbiter is now ok , the radeon transfers are ok and the communication with USB registers is OK = this enough to tell that the PCI bus has no problem, no ?... For me the PCI bus is NOW ok.
So, maybe a PLX setting is not ok... I hope we will advance very fast next week with Didier because he has reserved hollidays AFAIR.
Have Good End of Year 2011 ... on this dying planet...
|
[All messages in this thread] [Start new thread]
What's the anti-troll code?
That's your personal code to be able to add comments and messages on the dhs.nu site.
Don't have a code or forgot it? Fix it here.
|
