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Atari coding BBS
 
Re: Disabling 68030 PMMU + caches
Posted by: Klaz Feb,08.2012-09:35 

Hi George,

I know that code from ULS. :)

However, even when I really can't say to understand the 68030 MMU, I'm quite sure that this code works 'by chance' only. ;)

The new table address must not go into the tc, tt0 or tt1 registers.
It should go into the lower longword of the crp register.

For example if you look at the description of the tc register here:
http://mikro.naprvyraz.sk/docs/Coding/Atari/Maggie/MMU.TXT
it gets quite obvious.

I think it works because it's actually disabling the PMMU, it doesn't move the PMMU table to another address.
Bit 31 in the tc register controls PMMU on/off.
When you write an address into that register, bit 31 will be zero. The PMMU will be disabled and everything else is ignored.

Now the *real* strange thing is that your code obviously also works with CPU caches on. ;)
Seeing that ULS disables the CPU caches when executin some of its core routines, I think I'll have to investigate in that direction.

Geez, I hate the PMMU! ;)

PS: I'm also using PMMU table copy when no memory protection has been detected.





[All messages in this thread]    [Start new thread]

Topic Posted by  Date 
Disabling 68030 PMMU + caches Klaz Feb,07.2012-10:55
  Re: Disabling 68030 PMMU + caches mikro Feb,07.2012-17:52
    Re: Disabling 68030 PMMU + caches Klaz Feb,07.2012-18:27
      Re: Disabling 68030 PMMU + caches ggn Feb,07.2012-19:28
        Re: Disabling 68030 PMMU + caches Klaz Feb,08.2012-09:35
          Re: Disabling 68030 PMMU + caches ggn Feb,09.2012-19:22
      Re: Disabling 68030 PMMU + caches mikro Feb,08.2012-12:08
        Re: Disabling 68030 PMMU + caches Klaz Feb,08.2012-13:44
          Re: Disabling 68030 PMMU + caches mikro Feb,08.2012-17:23
  Re: Disabling 68030 PMMU + caches Klaz Feb,09.2012-09:17
    Re: Disabling 68030 PMMU + caches sqward Feb,09.2012-16:01
      Re: Disabling 68030 PMMU + caches Klaz Feb,09.2012-16:37
      Re: Disabling 68030 PMMU + caches mikro Feb,10.2012-10:31


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