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Atari coding BBS
| Re: branch optimisation questi |
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Posted by: Creature XL
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Jun,28.2005-15:41
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It has a 5-state prediction ( the 1st Pentium has just 4 :). The miss-penalty is not so big as with P4 cause of the relatively small pipeline ( 4 stages). A misprediction is maybe 5 cylces, I dont find the correct number ATM, but it is stated somewhere in the MC68060 PDF. Modern processors ( the 060 aswell) have aswell something named "branch folding".
this means, that you dont have the target address assoziated to the branch-instruction adress in the Branche-Cache, instead the instruction word! therefore no instruction fetch is needed ( that is the reason for the 0-cycle branche mentioned in another post. But I dont find anything bout that in the 060 PDF, but in the Coldfire reports from freescale. the Coldfire seems to have exaclt the same caches ( I/ D/ Branch) as the 060. I am investigating further on the Branch-folding topic...
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Topic
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Posted by
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Date
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branch optimisation question
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gwem
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Jun,22.2005-00:15
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Re: branch optimisation question
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rdpkr
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Jun,22.2005-02:08
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Re: branch optimisation questi
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Peter
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Jun,22.2005-09:41
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Re: branch optimisation questi
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earx
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Jun,23.2005-15:45
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Re: branch optimisation questi
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gwem
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Jun,23.2005-17:49
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Re: branch optimisation questi
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earx
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Jun,24.2005-18:36
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Re: branch optimisation questi
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Creature XL
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Jun,25.2005-16:01
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Re: branch optimisation questi
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Creature XL
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Jun,25.2005-16:11
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Re: branch optimisation questi
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Leonard
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Jun,28.2005-14:54
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Re: branch optimisation questi
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Creature XL
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Jun,28.2005-15:41
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What's the anti-troll code?
That's your personal code to be able to add comments and messages on the dhs.nu site.
Don't have a code or forgot it? Fix it here.
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