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CT60 and related things BBS
| SDR refresh bug ! |
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Posted by: Didier Méquignon
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Jul,03.2003-18:01
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Hi Rodolphe has found a big bug inside the Xilinx SDR chip, this is a fast translation with altavista.
For info the CPUSHA instruction is used inside the Pexec for fulst caches after the reloctaion of the program. During this instruction and after there are lot of SDRAM access. So with this bug SDR not found some time for refresh the SDRAM chip (normally at each 15 uS) => data are lost and it's the crash.
Traduction Babel Fish
In English:
Indeed with the reading and writing anticipated to make of the 4111 and the 2111 I am obliged to look at if TS is inserted or not for stat the logical sequence of the ref..
But if the accesses are with the continuation, the end of the access precedes the TS, therefore I never have window for start a ref. makes some! It is very boring !! Because logic start with the TS, if not I am obliged to pass by again into 5111 and 3111 and one loses more than to pass from 2 pages to 1 page!
In fact well the CPUSH insane the shit but any other prog which would make too a long time full with access SDRAM in a consecutive way would make that the SDRAM would lose also electric charges....
This explains why certain DIMM are much better! The internal capacities flee less!! -)
Regard,
Didier.
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