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CT60 and related things BBS
| Re: IDE is finished |
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Posted by: Rodolphe
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Jan,29.2012-18:39
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All tests I did are 100% ok with PLX DMA to /from SDRAM.
Test L & M are running until the end (16M transfers !) with 0 errors
What can I test else ? I have only PCITEST to test.
If you can do or describe a test to let me see and capture the problem, it is nice.
My point of view is that IF the DMA PLX is able to READ and WRITE TO SDRAM 16 Millions times without errors, I do not see why the DMA PLX will not do that correctlyt just because he is taking the local bus to please the USB master instead of your order on the PCI TEST.
What the difference between PLX DMA R/W to/from SDRAM and PLX DMA R/W to/from SDRAM ??
;-)
PLX has not two different ways with diffent protocols and timings to access local bus !
By the way, the INT are OK too and I'd like to let you try them too with USB to let me know how it is running ...
I send you now the 3 last CPLD that you need to test.
All previous ones are not good and may give you USB problems in SDRAM, sure.
I did so many changments that I'm only sure about my last realease...
a+
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