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Atari coding BBS
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Posted by: Defjam
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Apr,22.2009-17:20
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It seems that I just fixed the problem...
I cleared the MFP-registers -after- the hbl-sync ... which is totally wrong, the MFP regs have to be cleared just before.
The sound stll seems to be quite ok.
Please note, that I use a modified version of SSD (will be released sometime later) - where all writes to the status-register are removed.
Timers/Irqs used:
SID: timer A,C,D
vbl,hbl & timer B
Some test-binary:
http://checkpoint.untergrund.net/defjam/topbott.zip
The main code of the current version:
;-------------------------------------------------------------------------------
topbottom_init: >PART
bsr wait_vbl
move #$2700,SR
move.l #rte_tb,$00000120.w
clr.b $FFFFFA1B.w
move.b #255,$FFFFFA21.w
bset #0,$FFFFFA07.w
bset #0,$FFFFFA13.w
bclr #3,$FFFFFA17.w ; auto eoi
move #$2300,SR
bsr wait_vbl
move.l #vbl_rout,$00000070.w
rts
ENDPART
;-------------------------------------------------------------------------------
vbl_rout: >PART
move #$2700,SR
move.w #32,$00000140.w
move.l #hbl,$00000068.w
move #$2100,SR ; hbl on
movem.l D0-A6,-(SP)
jsr MUSIC_ORG+4
movem.l (SP)+,D0-A6
move.b #$21,(SP) ; hbl on
addq.l #1,$00000466.w
rte
hbl:
subq.w #1,$00000140.w
bmi.s hbl_da
rte
hbl_da:
move #$2700,SR
move.l #hbl_sync,$00000068.w
move.b $FFFFFA13.w,reset_1+3 ; save mfp
move.b $FFFFFA15.w,reset_2+3 ; "
clr.b $FFFFFA13.w ; mfp lock
clr.b $FFFFFA15.w ; "
hdwait:
stop #$2100
bra.s hdwait
hbl_sync:
move #$2700,SR
addq.l #6,SP
move.l D0,-(SP)
moveq #24,D0
wait: dbra D0,wait
move.w #$0700,$FFFF8240.w
move.w #$0000,$FFFF8240.w
move.b #0,$FFFF820A.w ; 60 Hz
DS.W 16,$00004E71
move.b #2,$FFFF820A.w ;50 Hz
move.l #timer_b_bottom,$00000120.w
clr.b $FFFFFA1B.w
move.b #228,$FFFFFA21.w
move.b #8,$FFFFFA1B.w
reset_1: move.b #$12,$FFFFFA13.w ; restore mfp
reset_2: move.b #$34,$FFFFFA15.w ;
move.l (SP)+,D0
move.b #$23,(SP)
rte
ENDPART
timer_b_bottom: >PART
move #$2700,SR
clr.b $FFFFFA1B.w
move.b #$13,$FFFFFA21.w
move.b #8,$FFFFFA1B.w
move.w D0,-(SP)
move.b $FFFFFA21.w,D0
sync_tbu: cmp.b $FFFFFA21.w,D0
beq.s sync_tbu
move.b #0,$FFFF820A.w
DS.W 10+8,$00004E71 ;10
move.b #2,$FFFF820A.w
move #$2400,SR
move.w (SP)+,D0
move.l #rte_tb,$00000120.w
rte_tb:
clr.b $FFFFFA1B.w
rte
ENDPART
;-------------------------------------------------------------------------------
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