After this you are synced to 8 cycles accuracy or so, you need to further stabilize the synchro.
You do this with a small shifting that some clever guy came up with. So depending on the cycle state you got synced with, it shifts more or less to get into perfect syncro.
Here's a snippet from my demosystem macro for top border+hardsync.
http://files.dhs.nu/files_coding/hardsync.s
This is run at a Timer A interrupt with divide 4 and 97 data from start of VBL. See the demosystem for more details.
Looking at it now I can't tell why I put SR back to $2300 before the hardsync. It looks like a bug and should be just before the RTE :)